Quadrature stripping network



vMaly 2, 1961 Filed Oct. 25, 1956 G. WENNERBERG 2,982,867

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Filed 001;. 25, 1956 G. WENNERBERG QUADRATURE STRIPPING NETWORK '3 Sheets-Sheet 2 liza.- 7

@iff/@MJ lav/Vr May 2, 1961 G. wENNl-:RBERG 2,982,867

QUADRATURE STRIPPING NETWORK Filed Oct. 25, 1956 3 Sheets-Sheet 5 UnitedStates Patent-O ice l 239824861 Y Y i Y z f PatentedMay 2, 1961 and to the switching devices of the respective pairs. By 2,982,867 means of a reference voltage, the devices of each pair and QUADRATURE STRIPPING NETWORK Gunnar Wennerberg, Paciiic Palisades, Calif., assignol' to Lear, Incorporated, vSanta Monica, Calif.

Filed Oct. 25, 1956,'Ser. No. 618,368

. Claims. (Cl. 307-885) This invention relates to servo amplifiers operable in` also the input devices and output devices, are rendered alternately conducting. When each device coupled to the input circuit is conducting, the associated capacitor receives a charge representing a component of the signal the output circuit as a half cycle of a square wave, the

differences in the waveform of the input signals or the effect of quadrature components, and which is also capable of receiving D.C. inputs.

In many servo amplifier applications, a command signal comprising a modulated carrier wave is applied to the ampliiier to develop an outplut signal for use in moving a device to a desired position. senting the position of the device are applied to the ampli er to oppose the command signal. When the device is in the desired position, the command signal and follow-up signals should be equal in magnitude and opposite in phase. However, as is well known, it is rare that the two signals are truly opposite in phase under such'conditions, and a quadrature component exists which, if left uncorrected, would result inksaturation of the amplifier. In

addition, differences in the waveforms of the signals also tend to cause saturation of the 'amp-lilier. Attempts have been made to counteract or minimize the effects of quadrature and waveform variations, and have resulted iri the use of additional equipment, often of elaborate design,

lwhichv unduly tax space and weight limitations in aircraft.

l IIt is a iirst object of this invention to providean improved quadrature stripping-network in-which a*l substantially square wave output voltage corresponding to-input signals Vis developed with minimum delay; It is another object of this invention to provide a" quadramagnitude of which represents the average of the inphase component. A quadrature component in the input signal cannot effect the output, because a zero net charge on thercapacitor results therefrom; To develop half of the square wave, only one pair of switching devices and one storage Ielement are utilized.

The above and other objects and advantages of this invention will be apparent from the followingV descrip,- tion, taken in conjunction with the accompanying drawings, in which a preferred embodiment of the invention is Follow-up signals repre- Y illustrated by way of example.

. ings,

Fig. l is a schematic diagram of a quadrature stripping a net work employing diodes, in accordance with this invention, y.

Figs. 2 and 3 illust-rate wave forms to raid in explaining the operation of the network of Fig. `1,

Figs. 4 and 5 are schematic diagrams to illustrate vrespective modiiications of the diode arrangements.

Fig. 6 is a schematic diagram of avquadrature strippingl network employing transistors, further in accordance with this invention, v j

Fig. 7 is a schematic diagram illustrating a modification y of the network of Fig. 6 for developing a square waveoutput in response to either an AfC. or D.C. input, also in accordance with this invention,fand

Figs. 8a and 8b illustrates waveforms to'aid in explain` ing the operation of the circuit of Fig. 7.

Referring to Fig. l, a plurality of unilaterally conductive electron devices, illustrated as diodes, are arranged ture stripping network for producing a substantially square wave` voltage, wherein waveform` variations andlor quadrature elects in input signals produce no error in the shape of the square wave voltage, and characterized'by delay iin developing such voltage.. l

It is. still another object of this inventionf'to provide Acircuitrneans `to produce aI square wave voltage, which ignores'or is insensitive to waveform variations or 'quadrafor producing 'for producing ia square wave 4voltage from anr alternating lor -D.C. voltagef sourcewl:1ichI is unaffcted by Variations in wave form and the eifects of quad-` rature components of the AFC. voltage, and` which ,con-

' tributes to a servo amplifier system which is lighter inVY weight and occupies less` space that similar servo amplier systems. l

Briefly, a quadrature stripping network in4 accordance with the invention comprises two pairs of 'sfwitchingd/e vices, the devices of each pair 'being coupled respectively to an input circuit andan outputrcircuit, and "respective storage plements such as capacitors connected to ground 76'of an input transformer 78, to the primary winding 80 in'four sets 10, 12, 14 and 16. The diode sets vinclude two pairs of diodes each, 20-22 and 24-26, 28--30 and 32-34, 36-38 and 40-42, and'44-46 and 48-50.

The diodes of each pair are connectedin series,l and the pairs in each set are arranged in paral1e`1with .the diodes of one pair being inback-to-baclc' relationship with'the other pair.' As illustrated, the setsV 10, .12, 14, 16.are connected between the .terminals of respective'secondary '3 .windings 52, 54, 56,58 of a transformer60, and in series with `respective resistors 62 64, 66, and'68 4which serve as current-limitingmeans. 1 Y

The junctions 70, 72 of the respective pairs of diodes 20--22 and 36-.38 of twosets 10,` 14 are connected to-A gether and to one terminal 74 of Ithe secondary winding of which cyclical voltages maybe applied. As indi, cated, one terminal of each of primaryf and secondary ground potential. In a similar manner,th'e junctions86,

windings 76, 80 is connectedto afpoint of reference` or i' sets 12, 16'are connected togethery and to the Yprimary pairs 24-26, 2s-3o 1. f Reference will'cbe made Jto' Figli i' in'describinglthen'operationofthecircuit 'of Fig; 1.

winding ofan output transformer 92jthe secondary winding 94 of which may be coupled to a'square waye uti.- j lization device (notshown). Thetwo storage elexijints,l

represented as capacitors '96, 93,I are" respectively' cone nected between ground and the junctions V100, 102'of iode q and 'junctions 104,' 106 kof pairs 40-42, 44-46. 'f

befvutilizedas desired.. i Fronifthe-foregoing it 3 reference or gating voltagelll of fixed frequency, eg., 400 cycles per second, is applied to the p-rimary winding 61 of transformer 60. Reference voltage lli) is illustrated as a square wave voltage; this form is preferred, but it will become apparent that reference voltages of dif- :ferent waveforms, e.g., sinusoidal, 'could a1so `be `-used. The secondary windings 52, S4, 56, 58 are so poled that on one half cycle of the reference voltage, the 'diode sets i yand i6 'are conducting and 'the diode sets i2 and 14 are non-conducting. On the succeeding Ahalf cycle, the diode sets and 16 are non-conducting and the diodes of sets 12 and ld are conducting. l

i The operation of the above circuit is based upon the fact' that' when a diode set is conducting, the respective junctions of the two pairs of diodes are at the `same potential. `For example, considering the' sets lil, 12 during conduction of set l0, diode pairs 20-22 and 24-26 form parallel paths between which current ilow through secondary winding 56 and resistor V65, due to the reference voltage 110, is split. Thus, assuming thefdiodes are of the sametype, junctions 70 and i90, being theirnidpoints of the respective paths,will be at the same potential.' Upon application of a signal voltage of the fixed frequency to transformerii, and hence junction '716, the 'comp onents in phase with the reference voltage also appear at junction i60, whereupon capacitor 95 receives a 'corresponding net charge.V Since diode l?. is non-conducting, this charge is retained on capacitor 96. Qn the succeeding half cycle of the reference voltage, when s et 1t) 'is then cut on and set l2 rendered conducting, the junctions 102, 86 `areplace-d at the sarnepotential, for the reasons above explained. Thereupon, the charge on capacitor 96, which appears at junction 202, also appears 'at junction S6 and is applied to the output'transiorr'ner 92.

To further the understanding of the operation of the invention, attention is directed to Fig. 2, whereinrdotted curve 112 represents the signal voltage' from the input transformer 7S, which is of the same frequency as reference voltage/1li).v This signal voltage is `illustrated as 'composed of a sinusoidal component 114 which'is in phase with reference voltage H0, and afquadrature compone-nt H5., During the positive half cycle of the refer- 'ence voltage 110, capacitor 96 builds upa net charge, along a path generally represented by the dotted' line 113, which represents the average value of Jrhein-phase cornponent 114.. ofthe reference. voltage, the charge on capacitor 96 is transferred' to the output transformer 92. As illustrated, the charge `on capacitor 96, which is indicated at 120,

|`constitutes afpositive voltage representing the average value of the in-phase componentllt. i

.The charge on capacitor 96 is not affected ibythe quadrature componentw116.' As will be readily observed, the I equal positive and negative portions of this quadrature 'component willhavea net effect of zeroon the charge Yon capacitor 96. Thus, the circuit simplyignores. or is insensitive to the quadrature component. Meanwhile, while capacitor 96 is discharging, .a' charge of equal magnitude but'ppposite senseis beingbuilt up on capacitor `98,.along 'a path generally indicated by the 'dotted line 1,22. ,This charge is deliveredto output transl fo'rmer 92, during conduction of diodeset 16, asa negative voltage' 124`of magnitudecor'responding --to they averf 5 age value vof the in-phase component 114. The quadra- 5 ture component .116 does not affect the charge oncapaci- During thesucceeding negative half cycle tor `98, ,for the reason *above explained. Thus, the positiveY and lnegative 'voltages 120, v124 together-providea square wave'voltage applied tol-output transformer 92, to

l will-be.ajxp'arent thatthe above described circuit ignores or -isv insensitive to quadratureV components, in contrast to prior art circuits, such as so be known to-occur 'for the 2,982,867 A: a *j departs from a sinusoidal wave form as indicated. It will be readily apparent from'the foregoing that charges built up on the respective capacitors 96, 98 will represent the average value of the respective half cycles of the varying voltage 130, whereupon positive and negative voltages,

indicated at 120' and 124', are alternately applied to the output transformer 958 to form a square wave input thereto.

It will also beV notedthat the system-is insensitive to K .amplitude fluctuations in the line or reference voltage.

As long asl the amplitude of the reference voltage is greater than the input signal, the junctions of each diode set will lbe placed at the same potential on alternate half cycles, and the capacitors will be accurately charged and discharged in accordance with the irl-phase signal components,y i f j For maximum effectiveness of the above operation, transformer 7,8 Vis a relatively low impedance device, and transformer 92 is a high impedance device. Eurther, the input signal voltages `are of the same frequency as the reference voltage. Also, the reference voltages appearing across'k the secondary windings 52, 54, 56, 58 are greater than the signal voltages appearing across the secondary. winding 76 of input transformer '78. In this latter connection, the reference voltage applied to the output diode sets 12, 16 may be much lower than those applied to the input diode sets 10,- 14. The-reason will be apparent from a study ofFig. 2, i.e.,` the output diodesets 12, l16 accommodate only the charge voltages 120, 124, which are much smaller Vin magnitude than thesignal voltage i12 applied from input transformer 78:to vdiode sets 10, 14. Thus, by way ofvexample, transformer :60

maybe designed so that 60-volt peak reference voltagesy secondarywindings S4, 58 to enable diode sets 12,"16 to accommodatercharge voltages of, say, 20 volts. The'acl tual voltages would of rcourse be dictated `by ythe maximum values of the signal and charge voltages which will particular use to which the circuit' would be put. y 1 W The value ofthe' above circuitin a servo amplifier systerr'lwill be instantly apparent.v If two ,or more voltages are combined, in the manner previously indicated, and' applied toinput-transfo'rmer 78, any quadraturecomponent will be effectively stripped from' the composite signal, and the magnitude of the square WaveV output .voltage willy accurately represent the phase relationship of the thereof.

' An important n is that the total delay in developing the squarewave' is v only: a half cycle` ofthe'signal voltage,je.g., 0.625 milli- V second for yan input signal'of 800 cps. Th-isjcontrast'si. sharply with prior arrangementsrequiring filtering .to ob;l

tainsigniiicant Yquadrature rejection. "Filtering which aids in'reasonablel quadrature rejection may result in anlout- `putvoltage'which 'lags the cyclical input signal by many.

cycles; for example, for signals of 8G() c'.p.s. an RC tilter to effect` a :1 attenuation of quadrature components, and employing a resistor of 20,000 ohms and a capacitor i of 1 .0 microfarad capacitance, ywould result inthe output.

voltage lagging theV input signal by 12.5 'milliseconds ie., a delay of tenx(10) fullscycles of thesignal voltage.. l

advantage of the circuit of ,this invention" It will be recognized that each diode set above described is simply a switching means. Other switching arrangements could be utilized. For example, and referring'to Fig. 4, the diodes 24-26 of set 10 could be replaced wlth equal resistors 132, 134. Since the same voltage drop exists across the parallel paths comprising the series diodes 20-22 and series resistors 132-134, the mid-points of both paths,-i.e., junctions 70 and 100, will be at the same potential when the polarityof the reference voltage is proper for effecting conduction of diodes 20e-22. Again, therefore,any. signal voltage appearing at junction 70 will also appear at'junction 100. One diiverence here; of course, is that, during conduction of diodes .Z-22,;

the resistors 132-134 constitute high impedances for signal paths, and cause insertion loss which is .high compared to the extremely low insertion loss associated witl. Suc

an arrangement of two pairs of diodes as in Fig.1. insertion loss, however, may be maintained at a tolerable level by proper choice of resistors 132-134,'e.g., resistorsA having ofthe order of 1,000 or 2,000A ohms resistance. If some insertion loss can be tolerated, such an arrange ment permits the circuit to be constructed with half thev number of diodes used in the circuit of Fig. l.

Fig. illustrates still another arrangement wherein th diodes 22, 26 of set 10 are replaced by resistors 136, 138.

Junctions 70, 100 here are not at the mid-points of the.`

two paths, but are located at the same points in the respective paths; therefore, they are at the same potential when? the diodes 20, 24 are conducting. vrIn this arrangement,` in contrast to :the arrangements of Figs. 1 and 4, junctions 70, 100 are conductively connected to the reference voltage source `during `both portions of the reference voltage.;y For this reason, resistors 136, 138 are large, e.g., of the order of 0.2 megohm each, to provide high irripedance connections between the associated secondary winding and the junctions. Thus, although junction ltl'isconducfy tively connected to junction 7 0 at all times, a low impedance.. path for the signals is provided via `the diodes'Y when they are conducting, and a high impedance path through resistors136, 138 whenf the diodes are non-conducting. Under certain conditions, where smallleakage losses may be tolerated, such anarrangement represents another possibility where half the number of diodes4 in the circuit of Fig. l can be dispensed with.

. In the switching arrangement of Fig. 5, sincethe diodesare V.notfserially connected, resistors 136, 138 also serve. as current-limiting devices, whereby the current-limiting:-

resistor 66 (see Fig. l) can be eliminated.

.l Fig. 6 illustrates an arrangement wherein the switching i 'means comprise P-N-P junction transistors 141, 142, 143

and 144, which have respective emitter electrodes 146, 141/148,149, collector electrodes151, 152, 153, 154

and basesfelectrodes 156, 157, 15S, 159. The emitter` electrodes 146, 147 "are connected together, as are emitters 148, 149, and theirrespective junctions 160, V161vare connected tov capacitors 96, 98.' Transformer 60 is pro. vided with the center-tapped secondary windings 162, 163. g The halvesSZ, `56' of secondary'winding 162 correspond to secondary .windings 52, 56 of Fig. l, and are connected respectively between the collector and base electrodes 151 156 of transistor141 and the collector and baseele'ctrodes 1 153), v158 .of transistor 143, whereby the center-tap 164 base electrodes 152, 157 of 'transistorv 142 and the collectorand basefelectrodes'154, 159 of transistor 144. The` the primary Vv5vi1'1di1'1gf`90 "of outputY transformer 92 l' .l The conditions of operation are the same as foi-the circuit of Fig. 1, ,in that themagnitude of the reference voltage is greater than the ksignal voltages, the transistors' 141and 142, and also transistors 143, and 144, are rendered alternatelyconductiug, and transistors 141 and 143 conduct alternately. It has been found that each transistor will conduct when its base draws sucient current, and under these circumstances the emitter ofnsuch trani sistor is placed at the same potential as its collector. It is believed this results because thefpositiver potential at the base electrode, with .respectto the collector, effec-- tively short circuits the barrier layer between the emitter and collector` electrodes. Thus, on the half cycle of the reference voltagelwhen transistor 141 conducts, any iin-v phase component vof asignal appearing at junction pointY 16S-also appears at junction point 160, whereby capacitorv 96 is charged aspreviously explained. On the succeeding halfncycle oftherefer'ence voltage, transistor 142 conf ducts, .and the charge on capacitor 96is applied to junc-.f tion point "168 and Vto the primary winding 90 of output transformer 92,. Similarly,.transistors143, 144 cooperate to charge and discharge capacitor 98, whereby' a square" wave vvoltage lis applied to transformer*92.in.the.rnannerI of thecircuit'of Fig.1.'j A n 1 7,. Fig. 7 illustrates a modification ofthe circuit arrange ment of Fig.6,.wherein bothfA.-C. and D.C. input volt-.

vto which capacitor 96 is coupled; similarly',.collector electrodes l153and 1154 are connected together to provide al common junctionpoint 161,vto which capacitor 9,8 is coupled.. .Also connected between baseY electrodes 1 56, 157, andi-across theendv terminals ofV secondary winding.l

170, is va pair of resistors 172 and 174, the junction 1,75, f

of which isfdirectly connected to junctionpoint 160'; in-r asimilar mannen'a kpair of resistors176 and 178 con-L nected between ,base electrodes`158 and 159. have :their junction 179.-direc'tly" connectedto. junction point 161'.. The emitters'lf146, 148 f transistors 141, 143 are resistiye. ly connected, as j'through Ya pair-of .resistors l180, 182,.i which have 'equal'values'ofresistance VThe .emitters 147,t

.. 149 oftransistors 142, 144 are directly connectedtogether.

j' The positiveandnegative terminals of a D.C. sourcel are connectedljdirectly to the emitter electrodes 146, .148, ofvvtransisto'rs.141,143, to` provide,` means forv applying a. D.C. signal Lvoltage to the4 circuit. Cyclical signal voltav agespare applied through theprirnary winding 183 of,y al. tra/'n's'formerg1,8 4y which.v has its secondary winding 185 connectedzbetween the junction 186 of vresistors 180, 182.

' andthe junction 187 ofcapacitors96, 98'.'A Output signals center-tap 166 and` collectors 152, 154 are connected-tof are received byjtherseconda'ry winding 188 of -a trans.

y' former' 189 which has its primary winding 190 connected between the junction l 187, of. capacitors. 96', 98and the junction191 between the' emitter electrodes147,r149 of, transiswrsilftzrlst J -1 vIt will'be notedthat the emitter andbase electrode, con- L nections in 1j"`ig. -l'7v are the4 reverse of those illustratedA inl Fig. 6. In this connection, ithas been, foundthat the circuits will 'iiperate .satisfactprily whether the emitter elec-v` trodes orjthe collector electrodes of the .pairs of transis tors-v 1'41L142,f^1\4f"'-1,44k are directly connected,v f' j In the operationy f't'he circuit ofFig. 7, the secondary windings 170,f r i jellrefpoled,.as` indicated, s'crsp'that'the reference'f'pote`- als at the'rbase electrodes` 4156, 159 of,- transistors14'1, 144` arev of opposite polarity to the .po-z tenti-alger the base electrodes' 157, 515s of trans'isrdrsuz'; 143.' y*As in the-icasef of 'the transistors; of Figi 6,",.tl1ef` emitters "andfcollectors ofthe transistorswill be at the"V 'Y assess? `tmtepotential when their baseelectrodes are positive with respect to their collectors. Thus, when an A.C. voltage is applied to transformer 184 whiletransistor`141 isconducting, the in-phase components thereof-will be transferred from emitter 146 to junction point 160' to charge capacitor 96, and this charge is subsequently transferred through transistor 142, when it conducts, to appear across primary winding 190; capacitor 98 is similarly charged -and discharged, whereby a square wave output voltage is provided in the manner of the circuits'of Figs. land 6. 1

i Fig. 8a illustrates .the operation of the circuit ofl Fig. 7 in the presence of a D.C; voltage alone. In the arrangement of Fig. 7, the D.C. voltage appears at the emitter 146 of one input transistor 141 as a positive voltage 193, and vat the emitter 148 of the other input transistor 143 as a negative voltage 193. Since transistors. 141 and 143 are rendered alternately'conducting,by the reference voltage 110, the charge built up on capacitor 96 kduring theA positive half cycle of the reference voltage will be applied through transistor 142 to outputtransformer 1,89 during the following or negative half cycle of the reference voltage'. During such negative half cycle, capacitor 93 will be charged through transistor 143, which charge is applied through transistor V144 to the output transformer situation, las will be apparent `from inspection Vof the arl rangement of input transformer 184, a cyclical input signal will appear at Vemitters 146 and 15,8 as'cyclic-al signals 195, 195 superimposed upon the positive and negative'D.-C. voltages 193, 193'. Therefore, in the presence ofV cyclical input voltages which are sinusoidal and inv t receive acharge corresponding to Vthe sum of the nega-` tive'D.-C. voltage 193' and the negative half Vof the A.'C.` l Thus, a square wave output voltage 196 Will. befobtainedthe magnitude of the` half cycles'of which arefequal to half the applied D.C voltage, plus the aversignal 195..

age value of `a half cycle of lthe A.C. signal.

Although each of the circuits of Figs. 1,'6 and 7 have been illustrated and described for the productionofa cyclical or square wave output vvoltage;itwillrbe ap-y parent that either the switching -devices coupledto Vcapaci-Y tor 96, or thoseV coupled to capacitor 98, may ',be ernployed to produce unidirectional voltage pulseson either the positive or negative halves of the reference voltage.r If vsuch is done, it will of course be necessary .to replacerv the inductive load presented by the output ltratisfc'armerv with a resistive or capacitive load (-not shown) :in accordance'with wellknown principles.

l Although P-N-P junction transistors are illustrated andl described, it should be noted that N-P-N transistors ycould be employed, in which case the potentialswouldbereversed. A

Finally, it should be noted that capacitors 96,98 Vare' merely representativeas storage elements, and that other storage elements, e.g.', inductors, cou-ldv be used. If inductor storage elements were used,y respective high;v and low vimpedance circuitd means would of `course, be employedfforthe input v fcnitputcircuit means.

For the'foregoing, itk ill be apparenti tion provides anirnprovedquadrature stripping networkl employing switching Vmeans for charging and discharging a capacitor Vto obtain `a-squ'arepwave voltage .-in responseto signals, and in which asquarewavefvoltage in the presence of kA.C. signals lags such signals by only a half cycle thereof.

What is claimed is:

l. A quadrature stripping network comprising lirst and common junction point, a storage elementconnected be-J tween said common junction point and a point of reference potential, a source ofreference voltage of predetermined frequency, means coupling said rst and second switching devices to said source lfor rendering said switching devices alternately conducting, means for applying cyclical input signals of said predetermined frequency between the Ainput terminal of said first switching device and said pointof reference potential, saidoutput terminal of said'iirst switchingfdevice being atthe samepotential -as its input terminal during conduction thereof to effect storage of energy in said storage .element in the'presence of input signalr components inphase with the reference voltage, the output terminal of 'said second switching device being at the same potential as its input terminal during conduction thereof, whereby any energy stored in said storage element is transferred-to the output terminal thereof, and utilization means coupled to said output terminal. `2; The quadrature stripping network defined in claim l,

in which said first and second switching devices each include first and second pairs -of serially connected unidi're'ctionally conductive elements, the iirst and second pairs of unidirectional conductive elementsof each switching device being connected in parallel and'in back-toback relation with respect to each other,` andthe input and output terminals of each switching devicebeing the respective junctions of the iirst and second pairs of unidirectional conductivefelements thereof.

^ 3. The quadrature stripping network defined in claim l, in which the iirst and second switching devices comprise first and secondtransistors each having emitter, collector andbase electrodes, said reference voltage source being coupled 'between the baseelectrode and one of the remaining electrodesof each transistor, said ones `of the remaining electrodes of said transistors being the respective output and input terminals of said first and second switching devices, and the other-of the` remaining electrodes of said transistors respectively lbeing the'input and output terminalsfof iirst and second switching devices.

4. The quadrature stripping network-defined in claim l, in which said tirst and Vsecond switching devices-.each include first and second `pairs Yof serially connected circuit elements in parallel, the irst pairof circuit elements of each switching device including two diodes,v the .second pair of circuit elements of each switching device including a pair of resistors, said resistors; having equal values of resistance, the junctions of the-pairs ofdiodes forming the input terminals of said switching devices, Vand the niinals of said switching devices.

' 5./ The quadrature stripping networkl defined in claim l, inY which the first and second switching devices each includeua parallel arrangementy of two pairs vof circuit elements, eachvpair of circuit, elements including a diode and a resistorrconnected in series, said resistors having equal values of resistance, the/diodes in each parallel'arrangementbeing in back-to-backl relation, the junction of the` diodes and resistors of each switching device forming they input-and output terminals thereof, and said resistors presenting high impedancevv paths to signals during non-conduction of the diodes associated vrtherewith. f

mined `frequency to said switching-.devices 'to render 'them' alternately conducting, each of said switching devices having an inputtermi'nal andan outputterminal,

junctions of the pairs of resistors forming the output ter-fv the respective output terminal and input terminal of said first and second switching devices being directly connected to provide a common junction point, a capacitor storage element connected between said com-mon junction point and a point of reference potential, the output and input terminals of the respective s-witching devices being at the same potential during conduction thereof, means to apply input signals of said predetermined frequency between the input terminal of said first switching device and said point, the capacitor during conduction of said first switching device receiving a charge corresponding to the average values of only the components of the input signals that are in phase with the reference voltage, and said second switching device during conduction thereof effecting transfer to the output terminal thereof of the charge on said capacitor.

7. A quadrature stripping network comprising first, second, third and fourth switching devices each having input and output terminals, a source of cyclical reference voltage of predetermined frequency, said switching devices being coupled to said source, control means effecting simultaneous conduction of said first and fourth switching devices on one half cycle of the reference voltage and of said second and third switching devices on the succeeding half cycle of the reference voltage, a first capacitor connected between a point of reference potential and the respective output and input terminals of said first and second switching devices, a second capacitor connected between said point of reference potential and the respective output and input terminals of said third and fourth switching devices, each of said switching devices being characterized in that the output and input terminals thereof are at the same potential during its conduction, means to apply a cyclical input signal between said point of reference potential and the input terminals of said first and third switching devices, and output circuit means coupled to the output terminals of said second and fourth switching devices.

8. The quadrature stripping network defined in claim 7, in which said switching devices each include rst and second pairs of serially connected diodes, said first and second pairs of diodes being connected in a parallel circuit and being in back-toeback relation in said circuit, said control means applying the reference voltage across said parallel circuit, whereby during one half cycie of the reference voltage currents iiow through said first and second pairs of diodes simultaneously to place the respective junctions of said pairs of diodes at the same potential, said junctions of said first and second pairs of diodes forming the input and output terminals of the switching device, and said control means maintaining the reference voltage across said first and third switching devices at a level exceeding the peak Value of the input signals and across said second and fourth switching devices at a level exceeding the magnitude of any charge appearing on said first and second capacitors.

9. The quadrature stripping network defined in claim 7, in which said switching devices each include a transistor having emitter, collector and base electrodes, said control means applying the reference voltage between the collector and base electrodes of each switching device, said collector and emitter electrodes of each switching device forming the input and output terminals thereof, and said control means maintaining the reference voltage between the base and collector electrodes of said first and third switching devices at a value exceeding the peak value of the input signals and between the base and collector electrodes of said second and fourth switching devices at a value exceeding any charges on said first and second capacitors.

10. The quadrature stripping network defined in claim 9, in which said emitter and collector electrodes of each switching device respectively form the input and output terminals thereof.

11. The quadrature stripping network defined in claim.

l2. A quadrature stripping network comprising a pair of switching devices, each device having input and output terminals and characterized in that said terminals` are at the same potential when the device is conducting, the output terminal of said first device and the input terminal of said second device being directly connected to provide a common junction point, an energy storage element connected between said common junction point and a point of reference potential, means to apply a cyclical reference voltage of a predetermined frequency to said devices to render them alternately conducting, whereby the input and output terminals of said rst device are at the same potentialv during one half cycle of the reference voltage and the input and output terminals of said second device are at the same potential during the succeeding half cycle of the reference voltage, means to apply a cyclical input signal voltage of said predetermined frequency between the input terminal of said first device and said point of reference potential, said storage element during conduction of said first device receiving energy corresponding to the average value of components of the cyclical input signal voltage which are in phase with the reference voltage, said storage element receiving a net energy change of zero from quadrature components of the input signal voltage, and said second device during conduction thereof transferring the energy stored in said storage element to the output terminal thereof.

13. The quadrature stripping network defined in claim 11, including means to apply a D.C. voltage to the input terminal of said first switching device, said storage element during conduction of said lfirst switching device receiving energy corresponding to the magnitude and sense of said D.-C. voltage, and said second switching device during conduction thereof transferring the energy from said storage element to the output terminal thereof.

14. In combinaton, first and second Switching devices each having first and second terminals between which a controlled voltage may be applied, and input and output terminals, a direct connection between the respective output and input terminals of said rst and second switching devices, a storage element connected between said direct connection and a point of reference potential, means for applying a cyclical reference voltage between said point of reference potential and the first and second terminals of said first and second switching devices, said first switching device being characterized in that the input and output terminals thereof are at the same potential during one half cycle of the reference voltage, said second switching device being characterized in that the input and output terminals thereof are at the same potential during the succeeding half cycle yof the reference voltage, means coupled to the input terminal of said first switching device to apply thereto a cyclical input signal of the frequency of the reference voltage, and an output circuit coupled to the output terminal of said second switching device.

15. The combination defined in claim 13, in which one of said rst and second terminals of each switching device is directly connected to one of the input and output terminals thereof.

References Cited in the file of this patent UNITED STATES PATENTS OTHER REFERENCES Publication: Electronics, February 1956, pp. 178, 180, 1,82. 184, 186, 

